Semiconductor chip designers commonly write their circuit design definitions in a high-level design language, such as a register-transfer level (RTL) definition written in a standardized hardware-description language (HDL), for example Verilog or VHDL. This RTL circuit definition is synthesized automatically into a gate-level netlist. The process then continues, using the netlist, to physical design and layout.
While these activities are going on, verification and bug-fixing activities continue on the RTL design, leading to changes in the RTL circuit definition. Reflection of such changes in the netlist is called an ECO (Engineering Change Order). Re-synthesis of the entire netlist to reflect the change is a time-consuming and resource-intensive process. Therefore, when possible, engineers attempt to implement the ECO by making changes directly to the netlist.